HD64F3048F16 Datasheet, PDF (30/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
Table 1.1 Features
Feature
CPU
Memory
Interrupt
controller
Bus controller
Description
Upward-compatible with the H8/300 CPU at the object-code level
• General-register machine
 Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32-
bit registers)
• High-speed operation (flash memory version)
 Maximum clock rate: 25 MHz
 Add/subtract: 80 ns
 Multiply/divide: 560 ns
 16-Mbyte address space
• Instruction features
 8/16/32-bit data transfer, arithmetic, and logic instructions
 Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16
bits)
 Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16
bits)
 Bit accumulator function
 Bit manipulation instructions with register-indirect specification of bit
positions
• ROM: 128 kbytes
• RAM: 4 kbytes
• Seven external interrupt pins: NMI, IRQ₀ to IRQ₅
• 30 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
Rev. 3.00 Sep 27, 2006 page 2 of 872
REJ09B0325-0300