HD64F3048F16 Datasheet, PDF (82/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
After Execution of BCLR Instruction
Input/output
DDR
DR
P4
7
Output
1
1
P4
6
Output
1
0
P4
5
Output
1
0
P4
4
Output
1
0
P4
3
Output
1
0
P4
2
Output
1
0
P4
1
Output
1
0
P4
0
Input
0
0
Explanation of BCLR Instruction
To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-
only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to DDR to complete the BCLR instruction.
As a result, P4₀DDR is cleared to 0, making P4₀ an input pin. In addition, P4₇DDR and P4₆DDR
are set to 1, making P4₇ and P4₆ output pins.
The BCLR instruction can be used to clear flags in the internal I/O registers to 0. In an interrupt-
handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Rev. 3.00 Sep 27, 2006 page 54 of 872
REJ09B0325-0300