HD64F3048F16 Datasheet, PDF (666/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Clock Pulse Generator
19.5.3 Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t_cyc in the AC electrical characteristics. Note that φ_MIN must be in the lower
limit of the clock frequency range. Avoid settings that give system clock frequencies less than
the lower limit.
Table 19.6 shows the comparison with the clock frequency range for each version.
Table 19.6 Comparison with the Clock Frequency Ranges in the H8/3048 Group and
H8/3048B Group
ROM type
F-ZTAT
ZTAT
Mask ROM
Product type
H8/3048
F-ONE
H8/3048F
H8/3048
H8/3048
Mask
ROM
Version
H8/3047 H8/3045 H8/3044 H8/3048B
Mask Mask Mask _Mask
ROM ROM ROM _ROM
Version Version Version _Version
Guaranteed 4.5–5.5 V
clock
frequency _{3.15–5.5 V}
range
2–25
MHz
1–16
MHz
—
1–18
MHz
1–13
MHz
1–18 MHz
1–13 MHz
2–25
MHz
—
2.7–5.5 V
—
1–8
1–8
1–8 MHz
—
MHz
MHz
3.0–3.6 V 2–25
—
—
MHz
—
2–25
MHz
Crystal oscillation
range
2–25
MHz
2–16
MHz
2–18
MHz
2–18 MHz
2–25
MHz
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Rev. 3.00 Sep 27, 2006 page 638 of 872
REJ09B0325-0300