HD64F3048F16 Datasheet, PDF (155/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bits 7 to 0—Areas 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access to the corresponding address areas.
Bits 7 to 0:
ABW7 to ABW0
0
1
Description
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and
internal I/O registers is fixed and does not depend on ABWCR settings. These settings are
therefore meaningless in single-chip mode (mode 7).
6.2.2 Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
Initial value
Read/Write
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Areas 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0:
AST7 to AST0
0
1
Description
Areas 7 to 0 are accessed in two states
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
internal I/O registers are accessed in a fixed number of states that does not depend on ASTCR
settings. These settings are therefore meaningless in single-chip mode (mode 7).
Rev. 3.00 Sep 27, 2006 page 127 of 872
REJ09B0325-0300