HD64F3048F16 Datasheet, PDF (599/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17.2 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
UE NMIEG
1
0
R/W R/W
Section 17 RAM
1
0
 RAME
1
1

R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0: RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
Rev. 3.00 Sep 27, 2006 page 571 of 872
REJ09B0325-0300