HD64F3048F16 Datasheet, PDF (328/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for pins PA₇ to PA₀. While port
A acts as an output port, the value of this register is output. When a bit in PADDR is set to 1, if
port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is
cleared to 0, if port A is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
PA ₇
PA ₆
PA ₅
PA ₄
PA ₃
PA ₂
PA ₁
PA ₀
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Sep 27, 2006 page 300 of 872
REJ09B0325-0300