HD64F3048F16 Datasheet, PDF (327/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
9.11.2 Register Descriptions
Table 9.18 summarizes the registers of port A.
Table 9.18 Port A Registers
Address^* Name
Abbreviation R/W
H'FFD1
Port A data direction
PADDR
W
register
H'FFD3
Port A data register
PADR
R/W
Note: * Lower 16 bits of the address.
Initial Value
Modes
Modes
1, 2, 5, and 7 3, 4, and 6
H'00
H'80
H'00
H'00
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When
pins are used for TPC output, the corresponding PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA₇ DDR PA₆ DDR PA₅ DDR PA₄ DDR PA₃ DDR PA₂ DDR PA₁ DDR PA₀ DDR
Modes
3, 4,
Initial value
1
0
0
0
0
0
0
0
and 6 Read/Write 
W
W
W
W
W
W
W
Modes _{Initial value 0}
0
0
0
0
0
0
0
1, 2, 5,
and 7 Read/Write W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
While port A acts as an I/O port, a pin in port A becomes an output pin if the corresponding
PADDR bit is set to 1, and an input pin if this bit is cleared to 0. In modes 3, 4, and 6, PA₇DDR is
fixed at 1 and PA₇ functions as an address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
Rev. 3.00 Sep 27, 2006 page 299 of 872
REJ09B0325-0300