HD64F3048F16 Datasheet, PDF (131/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ₀ to IRQ₅ interrupt requests.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0

 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W
R/W
R/W R/W R/W
Reserved bits
IRQ ₅ to IRQ₀ enable
These bits enable or disable IRQ ₅ to IRQ₀ interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ₅ to IRQ₀ Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ₅ to
IRQ₀ interrupts.
Bits 5 to 0:
IRQ5E to IRQ0E
0
1
Description
IRQ₅ to IRQ₀ interrupts are disabled
IRQ₅ to IRQ₀ interrupts are enabled
(Initial value)
Rev. 3.00 Sep 27, 2006 page 103 of 872
REJ09B0325-0300