HD64F3048F16 Datasheet, PDF (87/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 2.13 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct (Rn)
Effective Address
Calculation
op rm rn
2
Register indirect (@ERn)
31
0
General register contents
op r
3
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
31
0
General register contents
op r
disp
Sign extension
disp
Section 2 CPU
Effective Address
Operand is general
register contents
23
0
23
0
4. Register indirect with post-increment
or pre-decrement
• Register indirect with post-increment @ERn+
31
0
23
0
General register contents
op r
1, 2, or 4
• Register indirect with pre-decrement @–ERn
31
0
General register contents
23
0
op r
1, 2, or 4
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Rev. 3.00 Sep 27, 2006 page 59 of 872
REJ09B0325-0300