HD64F3048F16 Datasheet, PDF (421/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Disabling of ITU Output by External Trigger
If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary
PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are
cleared to 0 in TOER, disabling ITU output. Figure 10.55 shows the timing.
φ
TIOCA₁ pin
Input capture
signal
TOER
N
H'C0
N
H'C0
ITU output
pins
ITU output
ITU output
N: Arbitrary setting (H'C1 to H'FF)
I/O port
Generic
input/output
ITU output
ITU output
I/O port
Generic
input/output
Figure 10.55 Timing of Disabling of ITU Output by External Trigger (Example)
Rev. 3.00 Sep 27, 2006 page 393 of 872
REJ09B0325-0300