HD64F3048F16 Datasheet, PDF (169/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bus cycle
T₁
T₂
T₃
φ
Address bus
CS _n
External address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Valid
Write
access
LWR
D₁₅ to D₈
Valid
D₇ to D ₀
Valid
Note: n = 7 to 0
Figure 6.8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
Rev. 3.00 Sep 27, 2006 page 141 of 872
REJ09B0325-0300