HD64F3048F16 Datasheet, PDF (600/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 RAM
17.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF10 to
H'FFF0F in the H8/3048B Group in modes 1, 2, 5, and 7, addresses H'FFEF10 to H'FFFF0F in the
H8/3048B Group in modes 3, 4, and 6 are directed to the on-chip RAM. In modes 1 to 6
(expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In
mode 7 (single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed:
read access always results in H'FF data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
Rev. 3.00 Sep 27, 2006 page 572 of 872
REJ09B0325-0300