HD64F3048F16 Datasheet, PDF (32/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
Feature
Programmable
timing pattern
controller (TPC)
Watchdog timer
(WDT),
1 channel
Serial
communication
interface (SCI),
2 channels
A/D converter
Description
• Maximum 16-bit pulse output, using ITU as time base
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
• Non-overlap mode available
• Output data can be transferred by DMAC
• Reset signal can be generated by overflow
• Usable as an interval timer
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
• Smart card interface functions added (SCI0 only)
• Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• A/D conversion can be externally triggered
D/A converter
I/O ports
Operating
modes
• Resolution: 8 bits
• Two channels
• D/A outputs can be sustained in software standby mode
• 70 input/output pins
• 8 input-only pins
• Seven MCU operating modes
Mode
Address Space Address Pins Initial Bus Width
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
1 Mbyte
1 Mbyte
16 Mbytes
16 Mbytes
1 Mbyte
16 Mbytes
1 Mbyte
A₁₉ to A₀
A₁₉ to A₀
A₂₃ to A₀
A₂₃ to A₀
A₁₉ to A₀
A₂₃ to A₀
—
8 bits
16 bits
8 bits
16 bits
8 bits
8 bits
—
Max. Bus Width
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
—
• On-chip ROM is disabled in modes 1 to 4
Rev. 3.00 Sep 27, 2006 page 4 of 872
REJ09B0325-0300