HD64F3048F16 Datasheet, PDF (475/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Watchdog Timer
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the versions with on-chip flash memory.
Bit 6
RSTOE
0
1
Description
Reset signal is not output externally
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
12.2.4 Notes on Register Rewriting
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR
These registers must be written by a word transfer instruction. They cannot be written by byte
instructions. Figure 12.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR
both have the same write address. The write data must be contained in the lower byte of the
written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for
TCSR). This transfers the write data from the lower byte to TCNT or TCSR.
TCNT write
Address
15
H'FFA8 *
H'5A
87
0
Write data
TCSR write
Address
15
H'FFA8 *
H'A5
87
0
Write data
Note: * Lower 16 bits of the address.
Figure 12.2 Format of Data Written to TCNT and TCSR
Rev. 3.00 Sep 27, 2006 page 447 of 872
REJ09B0325-0300