HD64F3048F16 Datasheet, PDF (280/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and
halts. DMAC operations continue in sleep mode. Figure 8.24 shows the timing of a cycle-steal
transfer in sleep mode.
CPU cycle
DMAC cycle
Sleep mode
DMAC cycle
T₂ T_d T₁ T₂ T₁ T₂
T_d T₁ T₂ T₁ T₂
T_d
φ
Address bus
RD
HWR , LWR
Figure 8.24 Timing of Cycle-Steal Transfer in Sleep Mode
Rev. 3.00 Sep 27, 2006 page 252 of 872
REJ09B0325-0300