HD64F3048F16 Datasheet, PDF (406/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Clearing Procedure for Complementary PWM Mode
Figure 10.34 shows the steps to clear complementary PWM mode.
Complementary PWM mode
Clear complementary PWM mode 1
Stop counter operation
2
1. Clear the CMD1 bit of TFCR to 0 to
set channels 3 and 4 to normal
operating mode.
2. After setting channels 3 and 4 to
normal operating mode, wait at least
one counter clock period, then clear
bits STR3 and STR4 of TSTR to 0 to
stop counter operation of TCNT3 and
TCNT4.
Normal operating mode
Figure 10.34 Clearing Procedure for Complementary PWM Mode
Rev. 3.00 Sep 27, 2006 page 378 of 872
REJ09B0325-0300