HD64F3048F16 Datasheet, PDF (257/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a
24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper
16 bits are all 1s. IOAR is not incremented or decremented.
Figure 8.6 illustrates how repeat mode operates.
Address T
Transfer
1 byte or word is
transferred per request
IOAR
Address B
Legend:
L = initial setting of MAR
N = initial setting of ETCRH and ETCRL
Address T = L
Address B = L + (−1)^{DTID •} (2^{DTSZ •} N − 1)
Figure 8.6 Operation in Repeat Mode
The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Rev. 3.00 Sep 27, 2006 page 229 of 872
REJ09B0325-0300