HD64F3048F16 Datasheet, PDF (34/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
MD2
MD1
MD0
EXTAL
XTAL
φ
STBY
RES
RESO/FWE^*1
NMI
P66/LWR
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
P84/CS0
P83/CS1/IRQ3
P82/CS2/IRQ2
P81/CS3/IRQ1
P80/RFSH/IRQ0
Port 3
Address bus
Data bus (upper)
Data bus (lower)
Port 4
H8/300H CPU
Interrupt controller
ROM
(mask ROM,
or flash
memory)
RAM
16-bit integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
DMA controller
(DMAC)
Refresh
controller
Watchdog timer
(WDT)
Serial communication
interface
(SCI) × 2 channels
A/D converter
D/A converter
P53/A19
P52/A18
P51/A17
P50/A16
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Port B
Port A
Port 7
Notes: 1. This pin functions as the FWE (input) pin on the H8/3048F-ONE (single power supply on-chip flash memory version). On
H8/300H Series versions with on-chip mask ROM it functions as the RESO (output) pin, and on dual power supply flash
memory versions (V_PP = 12 V) and on-chip PROM versions it functions as the RESO (output)/V_PP (input) pin.
2. Pin 1 on the H8/3048B Group which operates at 5 V is not used as the V_CC terminal, but is used as the V_CL terminal; the
external capacitor must be connected. Pin 1 is the V_CC pin on versions that operate on 3 V.
Figure 1.1 Block Diagram
Rev. 3.00 Sep 27, 2006 page 6 of 872
REJ09B0325-0300