HD64F3048F16 Datasheet, PDF (166/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
8-Bit, Two-State-Access Areas
Figure 6.5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper
address bus (D₁₅ to D₈) is used to access these areas. The LWR pin is always high. Wait states
cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
CSn
External address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
D₇ to D ₀
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.5 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Rev. 3.00 Sep 27, 2006 page 138 of 872
REJ09B0325-0300