HD64F3048F16 Datasheet, PDF (273/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
Figure 8.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
DMAC cycle
CPU cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T ₁
φ
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
Rev. 3.00 Sep 27, 2006 page 245 of 872
REJ09B0325-0300