HD64F3048F16 Datasheet, PDF (277/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.4.11 NMI Interrupts and DMAC
NMI interrupts do not affect DMAC operations in short address mode.
If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations.
In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI
input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the
bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME
bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting
the DTME bit to 1.
Figure 8.21 shows the procedure for resuming a DMA transfer in normal mode on channel 0 after
the transfer was halted by NMI input.
Resuming DMA transfer
in normal mode
1
DTE = 1
No
DTME = 0
Yes
Set DTME to 1
2
1. Check that DTE = 1 and DTME = 0.
2. Read DTCRB while DTME = 0,
then write 1 in the DTME bit.
DMA transfer continues
End
Figure 8.21 Procedure for Resuming a DMA Transfer Halted by NMI (Example)
For information about NMI interrupts in block transfer mode, see section 8.6.6, NMI Interrupts
and Block Transfer Mode.
Rev. 3.00 Sep 27, 2006 page 249 of 872
REJ09B0325-0300