HD64F3048F16 Datasheet, PDF (576/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 A/D Converter
Group
Selection
CH2
0
1
Channel Selection
CH1
CH0
0
0
1
1
0
1
0
0
1
1
0
1
Single Mode
AN (Initial value)
0
AN₁
AN₂
AN₃
AN₄
AN
5
AN
6
AN₇
Description
Scan Mode
AN
0
AN₀, AN₁
AN₀ to AN₂
AN₀ to AN₃
AN₄
AN , AN
4
5
AN to AN
4
6
AN₄ to AN₇
15.2.3 A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE







Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W







Reserved bits
Trigger enable
Enables or disables external triggering of A/D conversion
Reserved bit
Must not be set to 1
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7E by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7: TRGE
0
1
Description
A/D conversion cannot be externally triggered
(Initial value)
A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
Bits 6 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Reserved: Do not set to 1.
Rev. 3.00 Sep 27, 2006 page 548 of 872
REJ09B0325-0300