HD64F3048F16 Datasheet, PDF (470/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Watchdog Timer
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
Reset
(internal, external)
RSTCSR
Reset control
Clock
Clock
selector
Legend:
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Note: * Open-drain output pin
Figure 12.1 WDT Block Diagram
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
RESO^*
12.1.3 Pin Configuration
Output pins used by the WDT*¹ are shown in table 12.11.
Table 12.1 WDT Pins
Pin Name
Abbreviation I/O
Function
Reset output RESO
Output^*2
External output of watchdog timer reset signal
Notes: 1. Not provided in on-chip flash memory versions.
2. Open-drain output pin
Rev. 3.00 Sep 27, 2006 page 442 of 872
REJ09B0325-0300