HD64F3048F16 Datasheet, PDF (625/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Notes on Using the Boot Mode
1. When this LSI comes out of reset in boot mode, it measures the low period the input at the
SCI’s RXD₁ pin. The reset should end with RXD₁ high. After the reset ends, it takes about 100
states for this LSI to get ready to measure the low period of the RXD₁ input.
2. In boot mode, if any data has been written to the flash memory (if all data is not H'FF), all
flash memory blocks are erased. Therefore, this mode should be used for initial on-board
programming, or for forced recovery if the program to be activated in user program mode is
accidentally erased and user program mode cannot be executed, for example.
3. Interrupts cannot be used during programming or erasing of flash memory.
4. The RXD₁ and TXD₁ pins should be pulled up on the board.
5. This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing
the RE and TE bits in serial control register (SCR)) before branching to the transmit data
output pin. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the
TXD₁ is in the high level output state (P9DDR P9₁DDR=1, P9DR P9₁DR=1).
Before branching to the programming control program the value of the general registers in the
CPU are also undefined. Therefore, the general registers must be initialized immediately after
control branches to the programming control program. Since the stack pointer (SP) is
implicitly used during subroutine call, etc., a stack area must be specified for use by the
programming control program.
There are no other internal I/O registers in which the initial value is changed.
6. Transition to the boot mode executes a reset-start of this LSI after setting the MD₀ to MD₂,
FWE, and RXD1 pins according to the mode setting conditions shown in table 18.6.
At this time, this LSI latches the status of the mode pin inside the microcomputer to maintain
the boot mode status at the reset clear (startup from Low level to High level) timing*¹.
To clear boot mode, it is necessary to drive the FWE pin low during the reset, and then execute
reset release*¹. The following points must be noted:
• Before making a transition from the boot mode to the regular mode, the microcomputer
boot mode must be reset by reset input via the RES pin*¹. At this time, the RES pin must be
hold at low level for at least 20 system clock*².
• Do not change the input levels at the mode pins (MD₂ to MD₀) or the FWE pin while in
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. When a watchdog timer reset was generated in the boot mode, the
microcomputer mode is not reset and the on-chip boot program is restarted regardless of
the state of the mode pin.
Rev. 3.00 Sep 27, 2006 page 597 of 872
REJ09B0325-0300