HD64F3048F16 Datasheet, PDF (219/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Refresh Controller
Contention between RTCNT Write and Counter Clear
If a counter clear signal occurs in the T₃ state of an RTCNT write cycle, clearing of the counter
takes priority and the write is not performed. See figure 7.20.
RTCNT write cycle by CPU
T₁
T₂
T₃
φ
Address bus
RTCNT address
Internal
write signal
Counter
clear signal
RTCNT
N
H'00
Figure 7.20 Contention between RTCNT Write and Clear
Rev. 3.00 Sep 27, 2006 page 191 of 872
REJ09B0325-0300