HD64F3048F16 Datasheet, PDF (274/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
Figure 8.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
φ
DREQ
End of 1 block transfer
DMAC cycle
CPU cycle
DMAC cycle
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
Rev. 3.00 Sep 27, 2006 page 246 of 872
REJ09B0325-0300