HD64F3048F16 Datasheet, PDF (269/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.4.8 DMAC Bus Cycle
Figure 8.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T_d), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
CPU cycle
DMAC cycle (word transfer)
CPU cycle
φ
Address
bus
RD
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₁ T₂
Source
address
Destination address
HWR
LWR
Figure 8.13 DMA Transfer Bus Timing (Example)
Rev. 3.00 Sep 27, 2006 page 241 of 872
REJ09B0325-0300