HD64F3048F16 Datasheet, PDF (105/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Port 1
Port 2
A₇ to A₀
A₁₅ to A₈
A₇ to A₀
A₁₅ to A₈
A₇ to A₀
A₁₅ to A₈
A₇ to A₀
A₁₅ to A₈
P1₇ to P1₀^*2
P2₇ to P2₀^*2
P1₇ to P1₀^*2
P2₇ to P2₀^*2
P1₇ to P1₀
P2₇ to P2₀
Port 3 D₁₅ to D₈
D₁₅ to D₈
D₁₅ to D₈
D₁₅ to D₈
D₁₅ to D₈
D₁₅ to D₈
P3₇ to P3₀
Port 4 P4₇ to P4₀^*1 D₇ to D₀^*1
P4₇ to P4₀^*1 D₇ to D₀^*1
P4₇ to P4₀^*1 P4₇ to P4₀^*1 P4₇ to P4₀
Port 5 A₁₉ to A₁₆
A₁₉ to A₁₆
A₁₉ to A₁₆
A₁₉ to A₁₆
P5₃ to P5₀^*2 P5₃ to P5₀^*2 P5₃ to P5₀
Port A
PA₇ to PA₄
PA₇ to PA₄
PA₇ to PA₅^*3, PA₇ to PA₅^*3, PA₇ to PA₄
A₂₀
A₂₀
PA₇ to PA₅,
A₂₀^*3
PA₇ to PA₄
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P4₇ to P4₀ in 8-bit bus mode, and as D₇ to D₀ in 16-bit bus mode.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A₂₀ is always an address output pin. PA₇ to PA₅ are switched over to A₂₃ to
A₂₁ output by writing 0 in bits 7 to 5 of BRCR.
3.6 Memory Map in Each Operating Mode
Figure 3.1 shows a memory map of the H8/3048B Group. The address space is divided into eight
areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte
modes (modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range
specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also
differs.
Rev. 3.00 Sep 27, 2006 page 77 of 872
REJ09B0325-0300