HD64F3048F16 Datasheet, PDF (352/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channel 2
Figure 10.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1
output.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₂
TIOCB₂
IMIA2
IMIB2
OVI2
Module data bus
Legend:
TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
TCR2:
(16 bits × 2)
Timer control register 2 (8 bits)
TIOR2:
Timer I/O control register 2 (8 bits)
TIER2:
Timer interrupt enable register 2 (8 bits)
TSR2:
Timer status register 2 (8 bits)
Figure 10.3 Block Diagram of Channel 2
Rev. 3.00 Sep 27, 2006 page 324 of 872
REJ09B0325-0300