HD64F3048F16 Datasheet, PDF (480/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Watchdog Timer
12.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5 Usage Notes
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₃ state of a write cycle to TCNT, the write
takes priority and the timer count is not incremented. See figure 12.8.
Write cycle: CPU writes to TCNT
T₁
T₂
T₃
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Values
Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to
CKS0.
Rev. 3.00 Sep 27, 2006 page 452 of 872
REJ09B0325-0300