HD64F3048F16 Datasheet, PDF (170/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
16-Bit, Two-State-Access Areas
Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, two-state-access area. In
these areas, the upper address bus (D₁₅ to D₈) is used to access even addresses and the lower
address bus (D₇ to D₀) is used to access odd addresses. Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
CS _n
Even external address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
High
Valid
D₇ to D ₀
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
Rev. 3.00 Sep 27, 2006 page 142 of 872
REJ09B0325-0300