HD64F3048F16 Datasheet, PDF (102/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 20, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7: SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so
that the waiting time will be at least 7 ms at the system clock rate. For further information about
waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software
Standby Mode.
Bit 6: STS2
0
1
Bit 5: STS1
0
1
0
1
Bit 4: STS0
0
1
0
1
0
1
0
1
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
(Initial value)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3: UE
0
1
Description
UI bit in CCR is used as an interrupt mask bit
UI bit in CCR is used as a user bit
(Initial value)
Rev. 3.00 Sep 27, 2006 page 74 of 872
REJ09B0325-0300