HD64F3048F16 Datasheet, PDF (582/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 A/D Converter
15.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D
conversion timing. Table 15.4 indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 15.4.
In scan mode, the values given in table 15.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
φ
Address bus (2)
Write signal
Input sampling
timing
ADF
t_D
t _SPL
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t_D : Synchronization delay
t_SPL : Input sampling time
t_CONV: A/D conversion time
t _CONV
Figure 15.5 A/D Conversion Timing
Rev. 3.00 Sep 27, 2006 page 554 of 872
REJ09B0325-0300