HD64F3048F16 Datasheet, PDF (895/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix D Pin States
Reset in T3 State
Figure D.3 is a timing diagram for the case in which RES goes low during the T3 state of an
external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address
bus outputs are held during the T3 state.The same timing applies when a reset occurs in the T2
state of an access cycle to a two-state-access area.
Access to external address
T1
T2
T3
φ
RES
Internal
reset signal
Address bus
H'000000
CS₀
CS₇ to CS₁
AS
High-impedance
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
High-impedance
High-impedance
Figure D.3 Reset during Memory Access (Reset during T3 State)
Rev. 3.00 Sep 27, 2006 page 867 of 872
REJ09B0325-0300