HD64F3048F16 Datasheet, PDF (426/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.5.2 Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10.60 shows the timing.
TSR write cycle
T₁
T₂
T₃
φ
Address
TSR address
IMF, OVF
Figure 10.60 Timing of Clearing of Status Flags
10.5.3 Interrupt Sources and DMA Controller Activation
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 10.10 lists the interrupt sources.
Rev. 3.00 Sep 27, 2006 page 398 of 872
REJ09B0325-0300