HD64F3048F16 Datasheet, PDF (616/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.5.2 Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When
the on-chip flash memory is disabled, a read will return H'00.
Note: Bits 6 to 0 are reserved bits but are readable/writable.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7:
FLER
0
1
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset (RES pin or WDT reset) or hardware standby mode
(Initial value)
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting conditions]
• When flash memory is read during programming/erasing (including a vector read
or instruction fetch, but excluding a read of the RAM area overlapping flash
memory space)
• Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
handling)
• When a SLEEP instruction (including software standby) is executed during
programming/erasing
• When the bus is released during programming/erasing
Bits 6 to 0—Reserved: These bits are readable/writable.
Rev. 3.00 Sep 27, 2006 page 588 of 872
REJ09B0325-0300