HD64F3048F16 Datasheet, PDF (283/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
Enabling of DMAC
Yes
Interrupt hand-
ling by CPU
Selected interrupt
requested?
No
Clear selected interrupt’s
enable bit to 0
1. While the DTE bit is cleared to 0,
interrupt requests are sent to the
CPU.
2. Clear the interrupt enable bit to 0
1 ^{in the interrupt-generating on-chip}
supporting module.
3. Enable the DMAC.
4. Enable the DMAC-activating
interrupt.
2
Enable DMAC
3
Set selected interrupt’s
4
enable bit to 1
DMAC operates
Figure 8.26 Procedure for Enabling DMAC while On-Chip Supporting Module Is
Operating (Example)
If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 8.26 before and after setting the DTME bit to
1.
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next
interrupt does not occur before the DMA transfers end on all the activated channels. If the next
interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
Rev. 3.00 Sep 27, 2006 page 255 of 872
REJ09B0325-0300