HD64F3048F16 Datasheet, PDF (770/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Register
Address Register
(low) Name
Data
Bus
Width Bit 7
Bit 6
Bit 5
Bit Names
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'F0
Reserved area (access prohibited)
H'F1
H'F2
MDCR
8
SYSCR 8
—
—
—
—
—
SSBY STS2 STS1 STS0 UE
MDS2 MDS1
NMIEG —
MDS0
RAME
System
control
H'F3
BRCR
8
A23E A22E A21E —
—
—
—
BRLE Bus controller
H'F4
ISCR
8
—
—
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Interrupt
H'F5
IER
8
—
—
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E ^controller
H'F6
ISR
8
—
—
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
H'F7
Reserved area (access prohibited)
H'F8
IPRA
8
IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
H'F9
IPRB
8
IPRB7 IPRB6 IPRB5 —
IPRB3 IPRB2 IPRB1 —
H'FA Reserved area (access prohibited)
H'FB
H'FC
H'FD
H'FE
H'FF
Legend:
DMAC: DMA controller
ITU: 16-bit integrated timer unit
TPC: Programmable timing pattern controller
WDT: Watchdog timer
SCI: Serial communication interface
Notes: 1. The address depends on the output trigger setting.
2. For write access to TCSR TCNT, and RSTCR see section 12.2.4, Notes on Register
Rewriting.
3. Bits 6 to 0 in FLMCR2 are reserved bits but are readable/writable.
4. Byte data must be used to access FLMCR1, FLMCR2, EBR, and RAMCR.
Registers FLMCR1, FLMCR2, EBR, and RAMCR are implemented in the flash memory
version only. The mask ROM version does not have these registers.
Rev. 3.00 Sep 27, 2006 page 742 of 872
REJ09B0325-0300