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HD64F3048F16 Datasheet, PDF (270/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
Section 8 DMA Controller
Figure 8.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
DMAC cycle
CPU cycle
DMAC cycle
(last transfer cycle)
CPU cycle
T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2
φ
DREQ
Address
bus
RD
HWR , LWR
TEND
Source Destination
address address
Source Destination
address address
Figure 8.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
Rev. 3.00 Sep 27, 2006 page 242 of 872
REJ09B0325-0300