HD64F3048F16 Datasheet, PDF (146/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU.
φ
Internal
address bus
Internal
write signal
IMIEA
TIER write cycle by CPU
TIER address
IMIA exception handling
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
Rev. 3.00 Sep 27, 2006 page 118 of 872
REJ09B0325-0300