HD64F3048F16 Datasheet, PDF (449/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Programmable Timing Pattern Controller
11.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP₇ to TP₀). During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1
If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address
is H'FFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFA7
consists entirely of reserved bits that cannot be modified and are always read as 1.
Address H'FFA5
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFA7
Bit
7
6
5
4
3
2
1
0








Initial value
1
1
1
1
1
1
1
1
Read/Write








Reserved bits
Rev. 3.00 Sep 27, 2006 page 421 of 872
REJ09B0325-0300