HD64F3048F16 Datasheet, PDF (810/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Register
TCR0—Timer Control Register 0
H'64
ITU0
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
1
0
0
0
0
0
0
0

R/W R/W R/W R/W R/W R/W R/W
Timer prescaler 2 to 0
Bit 2 Bit 1 Bit 0
TPSC2 TPSC1 TPSC0 TCNT Clock Source
0
0
0 Internal clock: φ
1 Internal clock: φ/2
1
0 Internal clock: φ/4
1 Internal clock: φ/8
1
0
0 External clock A: TCLKA input
1 External clock B: TCLKB input
1
0 External clock C: TCLKC input
1 External clock D: TCLKD input
Clock edge 1 and 0
Bit 4 Bit 3
CKEG1 CKEG0 Counted Edges of External Clock
0
0 Rising edges counted
1 Falling edges counted
1
— Both edges counted
Counter clear 1 and 0
Bit 6 Bit 5
CCLR1 CCLR0 TCNT Clear Source
0
0 TCNT is not cleared
1 TCNT is cleared by GRA compare match or input capture
1
0 TCNT is cleared by GRB compare match or input capture
1 Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers
Rev. 3.00 Sep 27, 2006 page 782 of 872
REJ09B0325-0300