HD64F3048F16 Datasheet, PDF (153/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.1.3 Input/Output Pins
Table 6.1 summarizes the bus controller’s input/output pins.
Table 6.1 Bus Controller Pins
Name
Chip select 7 to 0
Address strobe
Abbreviation
CS₇ to CS₀
AS
I/O
Output
Output
Read
RD
Output
High write
HWR
Output
Low write
LWR
Output
Wait
WAIT
Bus request
BREQ
Bus acknowledge BACK
Input
Input
Output
Function
Strobe signals selecting areas 7 to 0
Strobe signal indicating valid address output
on the address bus
Strobe signal indicating reading from the
external address space
Strobe signal indicating writing to the
external address space, with valid data on
the upper data bus (D₁₅ to D₈)
Strobe signal indicating writing to the
external address space, with valid data on
the lower data bus (D to D )
7
0
Wait request signal for access to external
three-state-access areas
Request signal for releasing the bus to an
external device
Acknowledge signal indicating the bus is
released to an external device
Rev. 3.00 Sep 27, 2006 page 125 of 872
REJ09B0325-0300