SA1110 Datasheet, PDF (97/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
manager); all peripheral unit modules (DMA controller, LCD controller, serial controller 0-4); and
all memory controller resources. The PLL also remains in lock so that the part can be brought out
of idle mode quickly when an interrupt occurs.
9.5.2.1
Entering Idle Mode
Idle mode is entered while in run mode by executing a three instruction sequence consisting of the
privileged on-chip coprocessor 15 instruction ‘disable clock switching’, a load from a
noncacheable memory location (C=B=0), and the privileged on-chip coprocessor 15 instruction
‘wait for interrupt’. This sequence must reside in the first three words of an instruction cache line,
which requires that the linker align the idle mode instruction sequence on an eight word boundary.
Idle mode is entered by following the exact code sequence:
AREA  Idle$$Code , CODE, READONLY, ALIGN=5
mcr p15, 0, r0, c15, c2, 2
ldr r0, [r1]
mcr p15, 0, r0, c15, c8, 2
;Aligned to 8 word boundary
;p15 = coprocessor 15
;r0 = register 0 (contents not used)
;c15 = test, clk, and idle cntl register
;c2 = CRm = 0b0010
;2 = OPC_2 = 0b010
; r1 points to non-cachable mem loc
;c8 = CRm = 0b1000
9.5.2.2
Exiting Idle Mode
Any enabled interrupt from the system unit or peripheral unit causes a transition from idle mode
back to run mode. An interrupt is masked or unmasked using the Interrupt Controller Mask
Register (ICMR). The DIM (Disable Idle Mask) bit in the Interrupt Controller Control Register
(ICCR) controls which enabled interrupts bring the SA-1110 out of idle mode.
• When DIM=0, the ICMR register is ignored. Any enabled interrupt, masked or unmasked,
brings the SA-1110 out of idle mode.
• When DIM=1, the ICMR register is not ignored. Interrupts that are specifically enabled and
unmasked bring the SA-1110 out of idle mode.
Note: Refer to Section 9.2.1.5, “Interrupt Controller Control Register (ICCR)” on page 9-17 for detailed
information on the ICCR Disable Idle Mask bit.
When an interrupt occurs, the CPU clocks are reactivated, the wait-for-interrupt instruction is
completed, and run-program flow resumes.
If the interrupt bringing the SA-1110 out of idle mode is masked, program flow resumes in a linear
fashion. If the interrupt bringing the SA-1110 out of idle mode is unmasked, program flow
resumes as in any other interrupt service routine. You must reenable clock switching for both
circumstances.
A transition from idle to run mode also occurs when asserting the nRESET pin, or if OSMR 3 is
configured as a watchdog and a match occurs that causes the assertion of reset. Since the watchdog
timer (when enabled) is functional during idle, you must set the watchdog match register far
enough in advance to ensure that another interrupt is guaranteed to bring the SA-1110 out of idle
before the watchdog reset occurs. It is recommended that either an RTC alarm or another OS timer
channel be used for this purpose.
SA-1110 Developer’s Manual
9-27