SA1110 Datasheet, PDF (259/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
The external pins dedicated to this interface are TXD1 and RXD1. If serial transmission is not
required and both the GPCLK and UART are disabled, control of these pins is given to the
peripheral pin control (PPC) unit for use as general-purpose input/output pins (noninterruptible).
See the Section 11.13, “Peripheral Pin Controller (PPC)” on page 11-167.
Modem control signals (RTS, CTS, DTR, and DSR) are not provided in this block but can be
implemented using the general-purpose I/O port (GPIO) pins described in the Chapter 9, “System
Control Module”.
11.9.1
11.9.1.1
GPCLK Operation
Following reset, both the GPCLK and UART are disabled. This causes the Peripheral Pin
Controller (PPC) to assume control of the port’s pins. Reset causes the PPC to configure all of the
peripheral pins as inputs, including serial port 1’s transmit (TXD1) and receive (RXD1) pins.
Simultaneous Use of the UART and GPCLK
Serial port 1 contains a control bit to select which serial protocol to use: GPCLK or UART. Note
that the two protocols cannot be combined at the same time (GPCLK transmit and UART receive).
However, since the GPCLK and UART are fully independent blocks, a mode is supported that
allows the user to enable the GPCLK using serial port 1’s pins (TXD1 and RXD1).
The UART is enabled using two GPIO pins (GPIO<14> for transmit and GPIO<15> for receive
operation). This mode is enabled by setting the UART pin reassignment (UPR) control bit within
the peripheral pin controller (PPC). Section 11.13, “Peripheral Pin Controller (PPC)” on
page 11-167. Note that when this mode is enabled, serial port 1’s control bit, which selects GPCLK
versus UART operation, is ignored and serial port 1 defaults to GPCLK mode.”
11.9.2
11.9.2.1
11.9.2.2
GPCLK Control Register 0
GPCLK control register 0 (GPCLKR0) contains 3 bit fields that control various functions within the
GPCLK.
GPCLK/UART Select (SUS)
The GPCLK/UART select (SUS) bit is used to select whether serial port 1 is used for GPCLK or
UART operation. When SUS=0, GPCLK operation is selected. When SUS=0 control of the
transmit pin (TXD1) is given to the PPC unit; when SUS=0 control of the receive pin (RXD1) is
given to the PPC unit. When SUS=1, UART operation is selected and the state of all remaining
GPCLK register bits is ignored (remaining unchanged) and control of the TXD1 and RXD1 pins is
given to the UART. See the Section 11.11, “Serial Port 3 – UART” on page 11-109 for a
description of the programming and operation of serial port 1 as a UART. The SUS bit is the only
bit within the control register that is reset, placing serial port 1 into GPCLK mode while disabling
the transmitter and receiver.
Sample Clock Enable (SCE)
The sample clock enable (SCE) bit is used to enable or disable driving or receiving a clock using
GPIO pin 16. When SCE=0, the sample clock is disabled. When SCE=1, the sample clock is
enabled.
SA-1110 Developer’s Manual
11-79