SA1110 Datasheet, PDF (167/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Table 10-10. SMROM Command Encoding
Command ^{SDCKE SDCKE}
(at
(at
ncs
clock
clock
3:0
n-1)
n)
STOP
1
x
0
NOP
1
x
1
NOP
1
x
0
SA-1110 Pins
nSDRAS nSDCAS nWE
nOE
0
1
x
x
1
1
0
1
x
x
1
1
DRA12-0
x
x
x
10.5.11
SMROM State Machine
Figure 10-19 illustrates all possible SMROM controller states and transitions. Many of the states
are named after the SMROM commands with which they are coincident: they have a fixed duration
of one cycle. Transitions from the other states are determined by the overall memory controller
state and a few SMROM/SDRAM power-down/self-refresh status/control bits. Most of the states
and transitions may involve multiple SMROM devices. Only those states shown below "idle"
involve a single SMROM row. If none of the labeled transitions have their conditions satisfied and
no default transition is indicated, the current state is maintained for at least one more cycle.
Hardware or sleep reset causes the SMROM state machine to enter the "idle" state. Upon hardware
or sleep reset, the SA-1110 is compatible with the following SMROM default mode registers
settings: RAS latency of 2 cycles, CAS latency of 5 cycles, burst length of 4, and sequential burst
addressing. However, the mode registers must be written prior to attempting bursts (caches or read
buffer enabled). Writes to the SMCNFG register instigate one or two MRS commands (to one or
two bank pairs of SMROM. These MRS commands always change the burst length to 8; RAS
latency and CAS latency may change according to SMCNFG bits. As required to ensure high
impedance on SMROM data outputs, the SA-1110 holds nWE, SDCKE 0, and nOE high during
power-up.
If the SMROM_EN pin is held high, MDCAS00, SMCNFG:CL0, and SMCNFG:RL0 must
maintain their hardware or sleep reset values to avoid mismatches in RAS latency between the
SA-1110 and boot SMROM following a subsequent hardware or sleep reset.
The following prioritization is used for transitions out of the idle state. Some of these variables
merely stall the SMROM state machine while performing DRAM/SDRAM tasks. If enabled via
the MDREFR:EAPD and MDREFR:KAPD bits, the "Auto_Power_Down" transition occurs when
none of the higher priority transitions are asserted. The "Auto_Power_Up" transition occurs when
"New_Enable" or "New_Access" is asserted during the "power-down" state.
High priority - "Enter_Sleep"
"New_Enable"
"New_Access"
Low priority - "Auto_Power_Down"
When the internal system bus causes a new access, the state machine will execute an ACT
command. Then the SA-1110 executes one READ command for each single or burst access. For
burst-of-N transfers, (N-1) NOP commands follow the READ. Finally, a STOP command
terminates all transfers smaller than burst-of-eight. Figure 10-20 shows a timing diagram of an
SMROM transaction.
SA-1110 Developer’s Manual
10-53