SA1110 Datasheet, PDF (256/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
The following table shows the location of the top/bottom of the transmit/receive FIFOs in the UDC
data register (UDCDR). Note that both FIFOs are cleared when the SA-1110 is reset and when
UDD is written to zero. After either of these actions takes place, the user may prime the transmit
FIFO by writing up to sixteen 8-bit values to the UDCDR before enabling the UDC.
0h 8000 0028
UDCDR
Read/Write
7
6
5
4
3
2
1
0
Bottom of Receive FIFO
Reset
0
0
0
0
0
0
0
0
Read Access
7
6
5
4
3
2
1
0
Top of Transmit FIFO
Reset
0
0
0
0
0
0
0
0
Write Access
Bits
Name
Description
Top/bottom of transmit/receive FIFO data.
7..0
DATA _{Read – Bottom of receive FIFO data.}
Write – Top of transmit FIFO data.
11.8.13 UDC Status/Interrupt Register
The UDC status/interrupt register (UDCSR) contains bits that are used to generate the UDC’s
interrupt request. Each bit in the UDC status/interrupt register is logically ORed together to
produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC
status/interrupt register to determine why the interrupt occurred.
Every bit in the UDCSR is controlled by a mask bit in the UDC control register. The mask bits,
when set, will prevent a status bit in the UDCSR from being set. If the mask bit for a particular
status bit is cleared and an interruptible condition occurs, the status bit will be set. In order to clear
status bits, the CPU must write a one into the position that it wishes to clear. The interrupt request
for the UDC will remain active as long as the value of the UDCSR is non-zero.
11.8.13.1 Endpoint 0 Interrupt Request (EIR)
The endpoint 0 interrupt request will be set if the EIM bit in the UDC control register is cleared,
and in the UDC endpoint 0 control/status register, the OUT packet ready bit gets set, the IN packet
ready bit gets cleared, the data end bit gets cleared, the setup end bit gets set, or the sent STALL bit
gets set. The EIR bit is cleared by writing a one to it.
11.8.13.2 Receive Interrupt Request (RIR)
The receive interrupt request bit gets set if the RIM bit in the UDC control register is cleared and
the RPC bit in the UDC endpoint 1 control/status register gets set. The RIR bit is cleared by writing
a one to it.
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SA-1110 Developer’s Manual