SA1110 Datasheet, PDF (235/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8
Serial Port 0 – USB Device Controller
This section describes the implementation-specific options of the USB protocol for a device
controller as it applies to serial port 0, such as number, type, and function of the endpoints,
interrupts to the CPU, transmit/receive FIFO interface, and so on. It is assumed that the user has a
working knowledge of the USB standard. The UDC is USB-compliant and supports all standard
device requests issued by the host. For programmer convenience, summaries of UDC operation are
provided as well as quick reference tables. However, the user should refer to the Universal Serial
Bus Specification, Revision 1.0¹ for a full description of the USB protocol and its operation.
Serial port 0 is a universal serial bus device controller (UDC) that supports three endpoints and can
operate half-duplex at a baud rate of 12 Mbps (slave only, not a host or hub controller).
The serial information transmitted by the UDC contains layers of communication protocols, the most
basic of which are fields. UDC fields include: sync, packet identifier, address, endpoint, frame number,
data, and CRC fields. Fields are used to produce packets. Depending on the function of a packet, a
different combination and number of fields are used. Packet types include: token, start of frame, data,
and handshake packets. Packets are then assembled into groups to produce frames. These frames or
transactions fall into four groups: bulk, control, interrupt, and isochronous. (The UDC supports only
bulk and control.) Endpoint 0, by default, is used only to communicate control transactions to configure
the UDC after it is reset or hooked up (physically connected to an active USB host or hub). Endpoint 0’s
responsibilities include: connection, address assignment, endpoint configuration, bus enumeration, and
disconnect. Endpoint 1 is used to perform bulk OUT data transactions and receiving data from the USB
host; endpoint 2 is used to perform bulk IN data transactions and transmitting data to the USB host.
The UDC uses two separate FIFOs to buffer incoming and outgoing data to or from the host
(16-entry x 8-bit for transmitting, and 20-entry x 8-bit for receiving). The FIFOs can be filled or
emptied either by the DMA or the CPU, with service requests being signalled when either FIFO is
half-full or empty. Interrupts are signalled when the receive FIFO experiences an overrun and the
transmit FIFO experiences an underrun. The control endpoint 0 has an additional 8-entry x 8-bit
FIFO that can only be read or written by processor reads and writes.
The external pins dedicated to this interface are UDC+ and UDC-. The USB protocol uses
differential signalling between the two pins for half-duplex data transmission. A 1.5-Kohm pull-up
resistor is required to be connected to the USB cable’s D+ signal to pull the UDC+ pin high when
not driven. This signifies the UDC is a high-speed, 12-Mbps device and provides the correct
polarity for data transmission. Using differential signalling allows multiple states to be transmitted
on the serial bus. These states are combined to transmit data as well as various bus conditions,
including: idle, resume, start of packet, end of packet, disconnect, connect, and reset.
1. The latest revision of the Universal Serial Bus Specification Revision 1.0 can be accessed via the World Wide Web Internet site at:
http://www.teleport.com/~usb/
SA-1110 Developer’s Manual
11-55