SA1110 Datasheet, PDF (148/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
TDL2 field of MDCNFG. See Table 10-6 and Table 10-7 for a review of addressing, applicable to
all types of DRAM. The upper one or two bits of row address act as selects for SDRAM internal
banks.
10.4.4 SDRAM Commands
The SA-1110 accesses SDRAM by using the following subset of standard interface commands:
• Mode Register Set (MRS)
• Bank Activate (ACT)
• Read (READ)
• Read with Auto-Precharge (READAP)
• Write (WRIT)
• Write with Auto-Precharge (WRITEAP)
• Precharge All Banks (PALL)
• Auto-Refresh (CBR)
• Power-Down (PWRDN)
• Enter Self-Refresh (SLFRSH)
• Exit Power-Down (PWRDNX)
• No Operation (NOP)
Table 10-8 shows the SDRAM interface commands.
Table 10-8. SDRAM Command Encoding
Command
SDCKE
(at clock n-1)
PWRDN
1
SLFRSH
1
PWRDNX
0
CBR
1
MRS
1
ACT
1
READ
1
READAP
1
WRIT
1
WRITEAP
1
PALL
1
NOP
1
NOP
1
SDCKE
(at clock n)
0
0
1
1
x
x
x
x
x
x
x
x
x
nRAS/
nSDCS3:0
1
0
1
0
0
0
0
0
0
0
0
1
0
SA-1110 Pins
SDRAS SDCAS
1
1
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
1
x
x
1
1
nWE
nCAS/
DQM3:0
1 4’b1111
1 4’b0000
1 4’b1111
1 4’b0000
0 4’b1111
1 4’b1111
1x
1x
0 Mask
0 Mask
0 4’b1111
xx
1x
DRA14-11,
DRA9-0
DRA10
x
x
x
x
x
x
x
x
Mode
(DRA 14:7 = 8’b0
DRA 6:4 = {1’b0, TDL},
DRA 3 = 1’b0,
DRA 2:0 = 3’b000)
Bank, row
Bank, column 0
Bank, column 1
Bank, column 0
Bank, column 1
x
1
x
x
x
x
10-34
SA-1110 Developer’s Manual