SA1110 Datasheet, PDF (330/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
0h 8006 0018
MCP Status Register: MCSR
Read/Write and Read-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
000000000000000000000101????0000
(Sheet 2 of 2)
Bits
5
6
7
8
9
10
11
12
13
14
15
31..16
Name
ARO
TTU
TRO
ANF
ANE
TNF
TNE
CWC
CRC
ACE
TCE
—
Description
Audio receive FIFO overrun.
0 – Audio receive FIFO has not experienced an overrun.
1 – Audio receive logic attempted to place data into receive FIFO while it was full, request
interrupt.
Telecom transmit FIFO underrun.
0 – Telecom transmit FIFO has not experienced an underrun.
1 – Telecom transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt.
Telecom receive FIFO overrun.
0 – Telecom receive FIFO has not experienced an overrun.
1 – Telecom receive logic attempted to place data into receive FIFO while it was full,
request interrupt.
Audio transmit FIFO not full (read-only).
0 – Audio transmit FIFO is full.
1– Audio transmit FIFO is not full.
Audio receive FIFO not empty (read-only).
0 – Audio receive FIFO is empty.
1 – Audio receive FIFO is not empty.
Telecom transmit FIFO not full (read-only).
0 – Telecom transmit FIFO is full.
1 – Telecom transmit FIFO is not full.
Telecom receive FIFO not empty (read-only).
0 – Telecom receive FIFO is empty.
1 – Telecom receive FIFO is not empty.
Codec write completed (read-only).
0 – A write to a codec register has not completed since the last time this bit was cleared.
1 – A write to a codec register has been transmitted and has updated the register.
Codec read completed (read-only).
0 – The value read from the addressed codec register has not been returned to MCDR2.
1 – The value read from the addressed codec register is now in MCDR2.
Audio codec enabled (read-only).
0 – The audio codec input and output is disabled (bits 14 and 15 are 0 in Audio Control
Register B).
1 – Audio codec input and/or output is enabled (bits 14 and/or 15 is 1 in Audio Control
Register B).
Telecom codec enabled.
0 – The telecom codec input and output is disabled (bits 14 and 15 are 0 in Telecom
Control Register B).
1 – Telecom codec input and/or output is enabled (bits 14 and/or 15 is 1 in Telecom Control
Register B).
Reserved.
11-150
SA-1110 Developer’s Manual